In the field of computing, general purpose central processing devices often utilize some form of virtual memory. In this context, virtual memory can facilitate efficient operation of higher-order computer processes, such as application-level processes. This can be accomplished by providing one or more virtual address spaces for different processes executing on a computer. A virtual address space can facilitate interaction with device memory by way of a simplified address space, which contains code and data pertinent to one process, but that might be unrecognized or inapplicable to another process. Furthermore, the application-level process can utilize and reference the simplified address space (e.g., virtual memory) independent of where data or code is physically located on physical memory.
To operate an environment with virtual memory, components of a central processing device translate virtual addresses generated by a higher-order computer process into physical addresses that reference actual locations on a physical memory. The component of the central processing device that typically performs the address translation is referred to as a memory management component, or memory management unit. A particular virtual to physical translation can be stored in a lookup table for later reference by the memory management unit, to reduce overhead involved in repeating the particular virtual to physical translation.
Several physical characteristics are relevant to the efficiency or effectiveness of address translation. Latency, for instance, is a metric indicating an amount of time for a memory management unit to retrieve a physical address in response to receiving a virtual address. Aliasing refers to multiple virtual addresses being mapped to a single physical address. Aliasing can lead to problems in memory retrieval if an accurate association between virtual address and physical address is not maintained. Additionally, memory granularity refers to an amount of memory (e.g., kilobytes, megabytes, etc.) that can be independently mapped by the memory management unit. In some cases, multiple memory granularities can be supported by a central processing unit.
The introduction of cache memory over the past couple decades for computing devices has provided significant reduction in memory latency. Cache memory is much more quickly accessed by a central processor than system main memory. Accordingly, the more frequently the central processor can rely on cache memory for performing various memory operations, the better the performance in terms of latency and similar metrics. Likewise, for virtual environments, the reduced complexity of virtual address space can provide greater efficiency for higher-level processes, particularly when coupled with the reduced memory latency of cache memory. Ongoing development in cache systems are targeted toward further improvements for computing performance.